1. Field of the Invention
The present invention relates in general to phase locked loop circuitry. More particularly, the present invention relates to a linear all-digital phase locked loop for use in a digital communications network to provide a stable reference clock for a digital stream of pulses.
2. Description of the Prior Art
Various configurations of circuitry have previously been used to accomplish the phase locked loop function. The first and most common configuration is the analog phase locked loop (PLL) and comprises a digital phase comparator to receive the input signal and is followed by a pulse width demodulator to accomplish phase detection. The output signal from the pulse width demodulator is filtered, amplified and fed into a voltage controlled oscillator (VCO). The input signal to the VCO is a time varying voltage and is converted by the VCO to a proportional frequency. The output of the VCO is fed back to the phase comparator as a reference signal. A typical VCO in this circuit includes a varactor. By changing the reverse-bias voltage across the varactor, the impedance of the feedback network is changed and thus the resonant frequency of the oscillator is changed. The use of the varactor introduces a slight non-linearity to the transfer function of the VCO.
A second configuration is a random-walk digital phase locked loop (PLL) and comprises a sampler circuit which receives the input signal and is followed by an up/down counter. The output of the up/down counter provides an input to a divider which generates the PLL output. The PLL output is also feedback to the sampler circuit and the up/down counter as a reference signal. The sampler circuit determines whether the input signal is leading or lagging the reference signal and provides one output to the up/down counter if the input signal is leading and a second output to the up/down counter if the input signal is lagging. Depending upon the value output by the sampler, the up/down counter is incremented or decremented. When the up/down counter reaches its maximum value (2.sup.m-1), a divide by n+1 or n-1 occurs and the up/down counter is reset to its initial value. It has been shown that this configuration is suitable for simple frequency tracking (DC operation) but its AC characteristics, such as intrinsic (or internally generated) jitter and jitter gain, make it unsuitable for the function to be performed by the present invention.